FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as an insulation-gate transistor which allows a high packing density integration and effects a good holding of memory contents and which does not make soft errors induced by alpha-particle irradiation. Also the invention concerns such semiconductor devices serving as a semiconductor memory and a logic circuitry.
A remarkable development is under way in the field of high packing density integration of semiconductor memories, especially in the field of dynamic random access memory (hereinafter to be referred to as d-RAM) which refreshes its memory contents at certain time intervals. Recently, there have been placed on the market 64 kilo-bit d-RAMs, and development of 256 kilobit d-RAMs is under way. High packing density integration of d-RAMs whose circuit arrangement has gone to such an extreme end as will not be simplified easily any further than the "one transistor-one capacitor" type is attained only by making the sizes of the respective structural components extremely fine. Such a trend of development has given rise to the tendency for progressively shortening the distance between the source region and the drain region (hereinafter to be referred to as the channel length) in insulation-gate transistors (hereinafter to be referred to as MOS transistors). However, in case the channel length of such transistors is reduced, there arises the inconvenience that, even when the gate potential of the transistor is zero-biased in order to render the transistor non-conductive, there flows a leakage current between the source region and the drain region so that the memory contents will become extinguished in a very short period of time, and the device will not operate to serve as a memory.
In the currently practiced process of making LSI devices using silicon, it is often the case to arrange a MOS field effect transistor (hereinafter to be referred to as MOS-FET) which is a component of the LSI, in such way as mentioned in FIG. 1. In order to cause a high-speed operation, this MOS-FET is formed to have an n-channel structure. In FIG. 1 which represents a prior art device, a p type region 11 represents a substrate. Also, two main electrodes are provided in a symmetrical pattern, so that an n.sup.+ type region 12 represents, for example, a source region, and an n.sup.+ type region 13 represents, for example, a drain region. Numeral 14 represents a gate region serving as a controlling electrode which is comprised of an n.sup.+ type polysilicon, and which is formed by relying on a known usual process of manufacture. It should be understood that this n.sup.+ type polysilicon gate region may be substituted by a metal gate region such as aluminum, molybdenum and tungsten. Numeral 15 represents a gate oxide film, 16 a field oxide film, and 17 a PSG film. Numerals 12a and 13a represent a source electrode and a drain electrode, respectively, which are made of a metal such as aluminum. Numeral 18 represents a p.sup.+ type region which serves as a channel-stopper region for inhibiting the tendency of formation of a current channel between the field oxide film 16 and p type substrate 11. It should be understood here that the gate oxide film 15 and like films can locally contain a Si.sub.3 N.sub.4 film. Also, it is usual to provide a passivation film on the surface of the device shown in FIG. 1.
By using the MOS-FET having basically the arrangement as shown in FIG. 1, there may be formed a d-RAM cell, for example, the following two types of arrangements. Instead of providing an electrode directly on one of the two main electrode regions, for example, on the drain region 13 of this MOS-FET, there may be provided thereon an insulating film made of SiO.sub.2, and an electrode is provided via this insulating film. Alternatively, there may be provided an n.sup.+ type polysilicon layer on the drain region 13, and the surface of this polysilicon layer is oxidized for a very small distance to provide a thin oxide film (SiO.sub.2), and an electrode is provided on this oxide film. The former arrangement is such that a capacitor, i.e. a storage capacitor, is formed by the n.sup.+ type region 13, the insulating oxide film and the electrode 13a. The latter arrangement is such that a capacitor or a storage capacitor is formed by the electrode 13a, the oxide film and the n.sup.+ type polysilicon layer. Such arrangements each serves as a d-RAM cell comprising one transistor and one capacitor.
Experimental samples are made for two kinds of substrates and gate oxide films having two kinds of thicknesses T.sub.ox, using the same manufacturing parameters excepting the channel length L (mask level). The memory retention characteristics of these samples are evaluated, and the result is described hereinbelow. The source region 12 and the drain region 13 are formed by ion-implantation of arsenic (As, implantation voltage: 100 kV, dose: 1.times.10.sup.15 cm.sup.-2) to a depth of X.sub.j of about 0.5 .mu.m. Also, there is given a channel doping with boron (B, implantation voltage: 30 kV, dose: 3.times.10.sup.11 cm.sup.-2). The gate width is set at 100 .mu.m for each sample, and the thickness T.sub.ox of gate oxide film is set at 500 .ANG. and 1000 .ANG., respectively, and the resistivity .rho..sub.sub of the p type substrate 11 is set at about 7 .OMEGA.cm and about 20 .OMEGA.cm, respectively.
By the use of a circuit arrangement of the above-mentioned d-RAM having a terminal of its storage capacitor C.sub.s grounded as shown in FIG. 2, its memory retention characteristic is evaluated.
In FIG. 2, reference numeral 21 represents a word line, and 22 a bit line. Numeral 23 represents a MOS-FET T.sub.1, and 24 a storage capacitor C.sub.s. To effect "write-in", a write-in voltage V.sub.w is applied to the bit line 22, while a voltage V.sub.G is applied to the word line 21. In case this MOS-FET T.sub.1 is an n-channel type, these voltages V.sub.w and V.sub.G are positive voltages, respectively. When a positive voltage V.sub.w is applied to the bit line 22, it should be understood that when the MOS-FET T.sub.1 is rendered conductive by the application of a positive voltage V.sub.G to the word line 21, there flows a current to the storage capacitor C.sub.s, and this storage capacitor C.sub.s is charged to a value represented substantially by V.sub.w -V.sub.th, wherein V.sub.th represents a threshold voltage of the MOS-FET T.sub.1. In this state of the FET, electrons are allowed to flow out from the n.sup.+ type drain region 13 which serves as an electrode of storage capacitor C.sub.s, so that this region 13 is positively charged due to shortage of electrons therein. Then, the voltage V.sub.G of the word line 21 is set back to zero, and thereafter the voltage V.sub.w of the bit line 22 is removed. Whereupon, the write-in operation is completed. In the state that the memory contents are being retained, there is no need to apply an external voltage to any one of the terminals of the memory cell having the circuit arrangement of FIG. 2. As stated above, in this memory content holding state, the n.sup.+ type region 13 is short of electrons and is charged positive, and this n.sup.+ type region 13 is reverse biased relative to the p type substrate 11. This storing mode is called an electron-depletion storing mode. Accordingly, the contents of memory will be preserved for an extended period of time. The memory retention time in the electron-depletion storing mode is always longer than that in the electron-accumulation storing mode where the amount of excess electrons is stored in the n.sup.+ type storage region.
Although the biasing of the p type substrate 11 of the MOS-FET T.sub.1 has not been described with respect to FIG. 2, in case there is the fear that the contents of memory would become extinguished due to a sub-threshold current attributable to a shortened length of the effective channel of the MOS-FET T.sub.1, there is applied a substrate bias voltage, which is a negative voltage in this example, to prevent such extinguishment of the memory contents.
The memory content holding characteristic is measured in the manner as stated above. Such characteristic for three different samples is shown in FIGS. 3, 4 and 5, respectively. These data are observed in a d-RAM cell operating at room temperature. The applied voltages are: V.sub.G =5 V, and V.sub.w =5 V. The memory holding time means a period of time starting from the time at which the word line voltage is returned to zero up to the time when the voltage stored in the storage capacitor C.sub.s has dropped to about 1/2. The memory holding time is plotted as a function of the effective channel length L.sub.eff. This L.sub.eff should be noted to be shorter by about 0.5 .mu.m as compared with the channel length at mask level. In FIG. 3, marks 1, 2, 3 and 4 correspond to the substrate bias voltage of 0 V, -1 V, -2 V and -4 V, respectively. FIG. 3 shows the result of the sample with its gate oxide film has a thickness T.sub.ox =1000 .ANG. and the resistivity of the p type substrate is .rho..sub.sub =7 .OMEGA.cm. FIG. 4 is the result of a sample wherein T.sub.ox =500 .ANG. and .rho..sub.sub =7 .OMEGA.cm. FIG. 5 shows the result of a sample wherein T.sub.ox =500 .ANG., and .rho..sub.sub =20 .OMEGA.cm. In all of these samples, the depths of the n.sup.+ type source region and the n.sup.+ type drain region are invariably 0.5 .mu.m, and the doping amounts of the channels by implantation of boron (B) are identical such as 5.about.7.times.10.sup.16 cm.sup.-3. In case L.sub.eff is long, the memory holding time in each of these samples is long, being about 100 seconds. However, for a shorter L.sub.eff, the holding time sharply becomes shorter. In the sample of FIG. 5 in which L.sub.eff is 2.5 .mu.m, the result of observation is such that even by the application of a substrate bias voltage V.sub.sub, the memory holding time lasts no longer than about 100 .mu.sec. In other words, with respect to the sample shown in FIG. 5, it should be understood that unless L.sub.eff is 3.5 .mu.m or greater, the device will no longer operate as a d-RAM. On the other hand, with the sample shown in FIG. 3, it will be understood that, if the substrate bias voltage V.sub.sub is set at -4 V, the memory contents are held for a sufficient period of time, even if the effective channel length is reduced up to L.sub.eff =1.5 .mu.m. However, even in this sample shown in FIG. 3, in case the effective channel length is reduced to L.sub.eff =0.5 .mu.m, the device can no longer be used as a d-RAM. In the sample shown in FIG. 4, even when V.sub.sub =-4 V, the memory contents-holding time is noted to begin dropping when L.sub.eff =1.5 .mu.m.
As will be understood from the foregoing description of samples, in case the channel length is shortened for the purpose of improving the packing density, if the channel length is reduced to about L=1 .mu.m (L.sub.eff =about 0.5 .mu.m), the memory content holding time drops sharply so that the device will no longer be operated as a d-RAM.
Next, explanation will be made of the reasons for the phenomenon that, in case the channel length is reduced as shown in FIGS. 3 to 5, the memory contents become extinguished sharply. A reduced length of channel gives rise to the effect of lowering, due to the effect provided by the source and drain regions, the potential barrier which, in case the channel length is not shortened, serves to prevent the flow of electrons across the source region and the drain region. In a sample having a long channel, the height of the potential barrier in the channel region is controlled almost solely by both the gate voltage V.sub.G and the substrate voltage V.sub.sub. However, in case the length of channel is reduced, the potential barrier height will become controlled also by the source region potential and the drain region potential. In other words, a static induction effect which is noted in a static induction transistor (SIT) begins to appear in the device having a substantially reduced length of channel, so that a current will become allowed to flow across the source and the drain regions even without an application of a gate voltage. Such current will hereunder be called an SIT current or a sub-threshold current. In FIG. 6 will be shown the relationship between the drain current I.sub.d and the drain voltage V.sub.d (a voltage relative to the source voltage when the latter is zero) for the sample shown in FIG. 3 but wherein the channel length L at mask level is 1 .mu.m (L.sub.eff =0.5 .mu.m). The vertical axis represents the drain current I.sub.d, and the horizontal axis represents the drain voltage V.sub.d. FIG. 6 shows the fact that, even in case the gate voltage V.sub.G =0, there flows a current I.sub.d across the source and drain regions. It is needless to say that, when the magnitude of the negative substrate bias voltage V.sub.sub is augmented, the drain current I.sub.d will become smaller. That is, even when the gate voltage is set at V.sub.G =0, there will begin to flow a current across the source and drain regions when a certain amount of voltage is applied therebetween.
In a d-RAM which is in the state that a voltage V.sub.m =V.sub.w -V.sub.th is written in the storage capacitor C.sub.s and is stored therein, it should be understood that the voltage V.sub.m is being applied across the source and drain regions. Accordingly, there naturally flows such drain current I.sub.d as that shown in FIG. 6, and thereby the stored voltage decreases progressively. The process of reduction of the stored voltage due to the current flowing across the source and drain regions can be analyzed easily. Since the device may be expressed in an equivalent circuit as shown in FIG. 7, the voltage stored in the storage capacitor C.sub.s will attenuate by the current which flows through the MOS-FET T.sub.1. By designating the voltage of the storage capacitor C.sub.s as V, the process of attenuation of the voltage can be expressed by the following formula: ##EQU1## wherein t represents time.
As will be understood from FIG. 6, the subthreshold current I.sub.d varies substantially exponentially relative to the voltage of the storage capacitor. That is, the sub-threshold current can be expressed by I.sub.d =I.sub.0 e.sup..alpha.V, wherein I.sub.0 and .alpha. can vary depending on the substrate bias V.sub.sub. The abovementioned Formula (1) under an initial condition V.sub.0 =V.sub.m can be solved as follows: ##EQU2## The time required for V.sub.t to become 1/r of the initial voltage V.sub.m will be: ##EQU3## The value obtained from calculation on the basis of r=2, and the value obtained from actual measurement are shown in FIG. 8. In FIG. 8, the memory-holding time is plotted as a function of the substrate bias voltage. In this Figure, mark o represents the value of measurement, and mark + represents the value of calculation. It will be noted that these two kinds of values are substantially in agreement with each other. More particularly, the attenuation of the stored voltage for a device having a reduced channel length is brought about by the sub-threshold current flowing across the source and the drain regions. Next, comparison is made between FIG. 3 and FIG. 4. It will be noted that the memory-holding characteristic for a reduced channel device is poor with the sample shown in FIG. 4. In other words, the smaller the thickness T.sub.ox of the gate oxide film becomes, the more the memory-holding characteristic degradates. This relationship will be described briefly as follows.
Referring back to FIG. 1, the gate region 14 of the n-channel MOS-FET is formed most frequently with an n.sup.+ type polysilicon. A sectional construction taken in one-dimensional direction from the gate region 14 toward the p type substrate 11 is shown in FIG. 9. The thickness of the p type substrate 11 is indicated by d. The gate oxide film 15 has a dielectric constant .epsilon..sub.2 and the p type substrate 11 has a dielectric constant .epsilon..sub.1. The potential profile when a reverse bias voltage V.sub.a (including a built-in potential V.sub.bi) is applied across the p type substrate 11 and the n.sup.+ type gate electrode 14 is expressed by the formula: ##EQU4## wherein: V.sub.0 represents a voltage applied to the gate oxide film 15;
V.sub.sc represents a voltage applied to the p type substrate; PA1 N.sub.A represents an impurity concentration of the PA1 p type substrate 11; and PA1 q represents a unit charge.
From Formulas (4) and (5) , the width W of the depletion layer in the p type substrate 11 and the voltage V.sub.0 which is applied to the gate oxide film are obtained as follows: ##EQU5## Also, the intensities E.sub.0 and E.sub.s of electric fields in the gate oxide film 15 and in the p type region 11 are expressed as: ##EQU6## wherein: ##EQU7## and represents the width of the depletion layer when the voltage V.sub.a is applied solely to the p type substrate 11.
The potential distribution within the p type substrate 11 is shown in FIG. 10 where the thickness T.sub.ox of the gate oxide film is varied. This Figure represents the result when the gate potential is maintained at the same level of the source potential. The vertical axis represents the potential, and the horizontal axis represents the distance from the gate oxide film 15 up to the p type substrate 11. The Figure shows the state in which only a built-in potential V.sub.bi is applied, when the substrate bias voltage V.sub.sub =0. It should be noted here that V.sub.bi represents a built-in potential at the junction of the n.sup.+ type region and the p type region. The symbol 0 given at the vertical axis represents a source potential. When T.sub.ox =0, the potential profile takes the curve as indicated by 1, and the potential at the interface of the p type region is rendered to a same level as that of the source potential. As T.sub.ox increases, the potential at the interface of the oxide film will increase as indicated by 2. When T.sub.ox =.infin., i.e. when the oxide film has a substantially large thickness, the potential curve will assume constant patterns as shown by broken lines. Conversely, as T.sub.ox decreases, the interface potential approaches the potential of the source region. This means that electrons are allowed to enter easily into this lowered potential region from either the source region or the drain region, so that a current is thus allowed to flow.
The attempt to develop a short channel structure necessitates a further reduction of the thickness of the gate oxide film. As a result, the tendency that the surface potential drops and that accordingly the current is allowed to flow easily will become more conspicuous. Also, as the channel length is shortened further, the storage capacitance C.sub.s becomes smaller. At the same time therewith, the write-in voltage V.sub.w for writing-in the memory cell will decrease also. Since the electric charge Q which is .stored in the storage capacitor under the written-in state is given by C.sub.s V.sub.m, the value Q=C.sub.s V.sub.m also naturally decreases as the length of the channel decreases. In case the storage capacitor C.sub.s is formed with SiO.sub.2 of 300 .ANG. into 10 .mu.m square in size, the storage capacitance C.sub.s will be about 0.12 pF. The stored electric charge when V.sub.m of 5 V is stored on this C.sub.s will be: Q=C.sub.s V.sub.m =6.times.10.sup.-13 C, which represents about 3.times.10.sup.6 in number of the electrons stored or in number of shortage of electrons.
However, the energy of alpha-particles which are irradiated from the ceramic package or the like is said to be of the order of 5 MeV. When a single alpha-particle is irradiated within a semiconductor body, there will be produced about one million pairs of electrons and holes. This single alpha-particle which is irradiated constitutes an amount sufficient for cancelling out almost all of the electric charge which has been stored in the storage capacitor. In other words, even where other holding conditions are perfect, the electric charge which is being stored in the storage capacitor will become extinguished by the irradiation of only a single alpha-particle.